Charlie Howard
Sr Principal Electrical Engineer at Sierra Space
- Role
- Sr Principal Electrical Engineer at Sierra Space
- Location
- Erie, CO, US
- LinkedIn followers
- 500 followers
Experience
Sr Principal Electrical Engineer
Jun 2021 — Present
Electrical Integration Design Team (EIDT) Lead for Dream Chaser Mission level lead engineer for spacecraft electrical compatibility and electrical system to subsystem integration. Electrical architect for spacecraft including control system, communication, data acquisition, power generation / power distribution and channelization- Spearheaded development and flight release of 125+ electrical ICDs throughout Dream Chaser organization- Directly responsible for solving electrical interface issues between subsystems; mitigating over 500 identified issues (JIRA tickets) while protecting vehicle TCSR through rapid implementation of corrective actions - Primary reviewer for all vendor provided electrical designsSubject matter expert (SME) for Dream Chaser architecture, including fault tolerance and system management - Architectural development for HW vs SW fault management and system approach to SW co-development and verification- Primary reviewer for SW autonomy, including fault detection/isolation/recovery (FDIR)Owner of Fault Tolerance Verification Tool (FTVT) for program- Budget and technical manager for SW development effort to supports NASA safety verification closure- coordinating with FSW, subsytem SMEs and Safety to develop certified productElectrical harness SME (chief engineer delegate for all wiring diagram and wire harness releases)- Led the last 9 channelization releases; converging all released ICDs and verifying pinouts and electrical compatibility per interface - Authored document identifying methodology to provide separation of redundant functions and method to manage the verification to ensure proper routing of safety critical signals- Formalized processes for harness derating, EMI/crosstalk, shield termination Owner of programmable logic device management plan (PLDMP) for company- Review and enforce SDRL content with respect to PLDMP deliverables- Design review chair & primary reviewer for all PLD & FPGA designs
Education
The University of Texas at Arlington
MS
1993 — 1995
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