Charchica Agrawal

About Charchica Agrawal

CPU ll GPU ll ARVR ll AI/MLSoc MSEE(VLSI) with 12+ years of experience in Semiconductor industry with area of specialization in Computer and Graphics Architecture-Front End Verification of GPU, CPU, AI/ML Core Power Management, AHB/AXI Bus Protocol, Cache and Memory Systems, Page Table, TLBs-Test Planning, Test Bench architecture, Assertions, problem solving and debug, Directed and Constrained Random Verification experience with SystemVerilog using UVM, OVM, VMM-Coverage driven verification(code/functional/assertion coverage) Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting-Passionate about CPU, GPU, ML/AI-Dedicated, Self Starter, Self Learner and Independent-Good Collaborative and Communication skills-Strong Analytical/problem solving skills.•Languages & Tools :UVM, OVM, VMM, ARM, 8086, System Verilog/Verilog/VHDL, C, C++, OOPS, Perl •Simulators : Synopsys Verdi, NC Verilog, ModelSim VHDL/Verilog simulator.•Synthesizers: Synopsys Design Compiler.•Operating Systems : Unix, Linux.

Experience

1. Staff Verification Engineer

   Arm

   Apr 2024 — Present · US

   SoC Verification for AI project. SV, UVM, C/C++, Script for automation

Education

• Gitanjali Sangeet Mahavidyalaya

  Kathak Indian Classical DANCE, ARTS

  1987 — 1997

• Delhi Public School - India

  High School (Maths & Science)

  1989 — 2002

• Bhilai Institute of Technology (BIT), Durg

  Bachelor's (B.E.), ELECTRONICS and Telecommunication

  2002 — 2006

• San José State University

  Masters (MS), ELECTRONICS & Electricals - VLSI

  2007 — 2010