Channabasappa Jalagar
Senior Pre-Silicon Validation/Verification Engineer at Intel Corporation
- Role
- Senior Pre-silicon Validation Verification Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Senior Pre-silicon Validation Verification Engineer
Mar 2017 — Present · Bengaluru, IN
Education
Visvesvaraya Technological University
Bachelor of Engineering (B.E.), Electronics and Communications Engineering
2002 — 2006
Skills
- Rtl Design
- Verilog
- Dft
- Soc
- Vlsi
- Very-Large-Scale Integration (Vlsi)
- System Verilog
- Usb
- Modelsim
- Tcl
- Vhdl
- Perl
- Eda
- Functional Verification
- Systemverilog
- Formal Verification
- Vera
- Semiconductors
- Specman E
- Application-Specific Integrated Circuits (Asic)
- Specman
- Fpga
- Asic
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