Bala Chandru
Sr. AMS Layout Design Engineer @ Synopsys
- Role
- Sr Layout Design Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Bala Chandru
A Analog layout Engineer who have worked on 2nm, 3nm, 16nm, 22nm, 40nm & 55nm with TSMC, SF & GF.Strong knowledge in Cadence Virtuoso L & XL (EDA tool) in addition to PVS & Caliber (Verification tool).Good knowledge in IC fabrication process, signal flow, CMOS & circuit fundamentals.Productive techniques for Matching, Shielding, Area & parasitic reduction in design.Solid debugging skills in LVS, DRC, ERC, LUP, EM, IR, Density & Antenna issues.Stable experience in nanosheet FET, FINFET, SOI & planar FET technologies.
Experience
Sr Layout Design Engineer
Jun 2025 — Present · Bengaluru, IN
Education
Sri Krishna College of Technology
Bachelor of Engineering - BE
2016 — 2020
BMC matric higher secondary school
HSC
2014 — 2016
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