Chandrashekhar Patil
Lead ASIC Engneer at Cisco
- Role
- Lead Asic Design Engineer at Cisco
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Chandrashekhar Patil
24+ years of experience in the Semiconductor Industry, in physical design (Innovus/FC)…
Experience
Lead Asic Design Engineer
Sep 2013 — Present · Bengaluru, IN
Education
Karnatak University
BE
1993 — 1997
Indira Gandhi National Open University
PGDOM
2007 — 2008
Visvesvaraya Technological University
Doctor of Philosophy - PhD
2016 — 2023
Visvesvaraya Technological University
M.Tech
1997 — 1999
International Institute of Information Technology Hyderabad (IIITH)
Ph.D
2008 — 2010
Skills
- Tcl
- Verilog
- Asic
- Drc
- Soc
- Spice
- Physical Design
- Cmos
- Systemverilog
- Perl
- Physics
- Eda
- Rtl Design
- Debugging
- Logic Synthesis
- Device Physics
- Vlsi
- Ic
- Static Timing Analysis
- Tcl, Perl
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.