Chandrakanth Kadaverugu

About Chandrakanth Kadaverugu

Physical Design Engineer with 8 years of experience, specializing in synthesis, floor planning, power planning, placement, clock tree synthesis (CTS), and routing. Proven track record in designing complex components like HBM PHY, test chips for SerDes evaluation, and ASIC digital blocks within FPGA environments.Experienced in advanced technology nodes, including 18A, 2nm, 3nm, 5nm, 7nm, 10nm, 11nm, and 16nm across major foundries like Intel IFS, TSMC, GlobalFoundries, and Samsung. Possesses a strong foundation in full-chip physical design implementation, partitioning, and pin planning, with skills in timing ECO creation, manual DRC fixes, EM/IR issue resolution, and applying metal ECOs on base-taped-out blocks.Well-versed in emerging methodologies for 2.5D and 3D physical design implementations, with proficiency in congestion analysis, DRC convergence, and driving PPA improvements. Expert in identifying and resolving inconsistencies in timing and parasitic parameters across all stages of the RTL-to-GDS flow.

Experience

1. Senior Staff Engineer, R & d

   新思科技股份有限公司

   Feb 2025 — Present

   3DIC Multi-Die Implementation using 3Dblox with expertise in die-to-die integration, floorplanning, physical design, and optimization across heterogeneous dies. EMIR, Thermal and STA.

Education

• MLR Institute of Technology

  Bachelor of Technology - BTech, Electrical, Electronic and Communications Engineering Technology/Technician

  2012 — 2016