Chandrakanth Betageri
Ip Design Verification Engineer @Intel
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WORK HISTORY
Ip Design Verification Engineer @Intel
Santa Clara, CA, US
As a senior verification engineer I am responsible for verification of power management IP for Intel Xeon server platform SoCs. I am responsible for RAS Error validation, Idle PM flows, Pchannel Protocol verification, one bit serial link protocol verification within power management IP.
EDUCATION
Basaveshwar Engineering College (A), Bagalkote
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
RV College Of Engineering
Master of Technology - MTech, VLSI Design and Embedded Systems
ABOUT CHANDRAKANTH BETAGERI
10+ years of experience in IP and SOC verification. Major areas include- IP verification cycle from writing the testplan to cover the all the functionality as per specification to verification signoff with different components like scoreboard, checker, monitors and functional coverage closure- Hands-on Systemverilog and Verilog- Hands on OVM/UVM methodology- Code and functional Coverage- Assertion based verification- Formal Verification
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