Chandrakant Jayanti
- Role
- Senior Lead Engineer at Qualcomm
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Chandrakant Jayanti
Expertise in handling multi-domain UPFs/DFT coverage/low power design/timing closure…
Experience
Senior Lead Engineer
May 2017 — Present
Microarchitecture development and specification. System Verilog and Verilog based RTL coding. Low power design for DSP and ARM V9 sub-systems. Clock controller design including integration of Ghz frequency PLLs UPF development for multi-power domain block according to the power spec. Validation of UPF using Conformal Low Power tool at RTL and Gate Level. Lint, CDC checks. Timing closure for high-speed design. Functional, performance, FPGA and Silicon validation support. Silicon bring-up and debug support using standard debug tools like scan-dump.
Skills
- Rtl Design
- Embedded Systems
- C
- C++
- Matlab
- Debugging
- Fpga
- Amba Ahb
- Vlsi
- Verilog
- System Verilog
- Vhdl
- Modelsim
- Microcontrollers
- Axi
- Integrated Circuit Design
- Xilinx
- System Design
- Simulations
- Uvm
- Amba Apb
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