Chandana Ray
Actively seeking Full-time in CPU/GPU/Memory/Interconnect/NOC RTL Design roles | Video/CVP RTL Design Intern @Qualcomm | ATOM Circuit Design Intern @Intel|Grad Student at NCSU | Ex-Qualcomm
- Role
- Video Cvp Rtl Design Intern at Qualcomm
- Location
- Raleigh, NC, US
- LinkedIn followers
- 500 followers
About Chandana Ray
Currently pursuing Master\'s in Electrical and Computer Engineering at the North Carolina State University specializing in Computer Architecture. Research Interests: Computer Architecture, CPU-microarchitecture Interested in job roles involving CPU and GPU microarchitecture, ASIC Design(RTL) Engineer, Design Verification Previous role: Layout Design Engineer, Qualcomm. At Qualcomm: I\'m very good in analyzing complex network circuits in Electronics. A glance of my experience summary: Technology Nodes : TSMC- 4nm, 16nm, 20nm Samsung- 5nm, 7nm, 8nm Intel - 10nm, 14nm Tools : Mentor Graphics, Genesys, MATLAB Layout Editor : Cadence Virtuoso EXL/ XL Layout Verification : PVS,Calibre and Assura EM-IR - Totem tool Scripting : PERL and SKILL coding Good knowledge of Analog and Digital Signal Layout Design. Experienced in hierarchical design implementation of floorplan, multiple block integration, signal and power routing at Chip level. Worked on Different analog Blocks like PM_TOP, ADC, PLL, BGR, LDO, CLK divider, TX and Rx blocks. Experienced in Physical Verification Checks - DRC, LVS, ERC, Antenna, LDL, under bump density and Float checks at Chip level. Apart from this, I\'m a quick learner and adaptable to any projects related to my domain which covers my strength and talent as well.
Experience
Video Cvp Rtl Design Intern
May 2023 — Present · Santa Clara, CA, US
Education
Kendriya Vidyalaya
12th, Science
2010 — 2012
Silicon Institute of Technology (SIT), Bhubaneswar
Bachelor of Technology - BTech, Applied Electronics and Instrumentation(AEI)
2012 — 2016
North Carolina State University
Master of Science - MS, Computer Engineering
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