Chandan K

About Chandan K

Exceptionally talented Engineer with hands on experience on cutting edge technology(4 nm).Certified courses in VLSI Physical Design from Synopsys,Mentor graphics and cadence training partner(IIVDT).M.Tech in VLSI Design.Highly motivated,Creative and versatile engineer with hands-on experience on cadence and Synopsys based Physical design flow especially skilled in timing analysis.

Experience

1. Senior Staff Engineer

   Qualcomm

   Dec 2024 — Present · IN

Education

• New Horizon college of Engineering-Bangalore, under Visvesvaraya Technological University

  M.Tech, VLSI Design and Embedded systems

  2010 — 2012

• BGSIT

  B.E., Electronics and communication

  2005 — 2009

• St,Philomenas PUC college,Mysore

  P.U.C, P.C.M.B

  2003 — 2005

Skills

• Clock Tree Synthesis
• Static Timing Analysis
• Digital Electronics
• Complete Asic Design Based on Cadence Flow
• Cadence Virtuoso Layout Editor
• Engineering Change Order
• Dft
• Cmos
• Floorplanning
• Lvs
• Cadence
• System Verilog
• Analog Circuit Design
• Rtl Design
• Ovm
• Timing Closure
• Powerplannig
• Ncsim
• Cadence Virtuoso
• Vlsi Verification
• Cadence Virtuoso Xl
• Uvm
• Spice
• Logic Design
• Rtl Verification
• Ncverilog
• Modelsim
• Xilinx
• Systemverilog
• Physical Design
• Soc Encounter
• Verilog
• Integrated Circuit Design
• Xilinx Ise
• Rtl Compiler
• Voltage Storm
• Simvision
• Amba Ahb
• Drc
• Encounter