Chanchal Chaurasia
Analog Circuit Design Engineer
- Role
- Analog Validation Engineer at 恩智浦半导体
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Chanchal Chaurasia
Analog Circuit Design Engineer | PLL | SERDES | LDO | LVDS | VLSI Design I am…
Experience
Analog Validation Engineer
Jan 2025 — Present · Bangalore, IN
Responsible for Design enablement configuration of the IP on reliability part, with different working environments, different aging engines and conditions.
Education
Banasthali Vidyapith
M.Tech, VLSI design
2015 — 2017
Indian Institute of Technology, Hyderabad
Intern, Analog IC Design
2016 — 2017
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.