Challen Yee

About Challen Yee

VETERAN IC MASK LAYOUT DESIGNER/ENGINEER Challen has a history involved with special memory and image processing IC products, mixed-signal, analog circuits, CMOS, BiCMOS, Dram, 0.25 um to FinFET technology, project leading, managing, hiring, training, mentoring, and developing methodology since 1990. Some highlights of his career was being instrumental in building a layout group and technical infrastructure at Mosys, Inc. remaining hands on all the way and taking the company public. He was also the solo designer for a company\'s first high performance RAMDAC. He is a member of a small and remarkably capable design team responsible for the successful first run silicon for a proprietary CMOS BSI imagining chip used in a first ever desktop protein sequencing platform. In the position, he is able to exercise his many facets for layout design including: floorplanning, verification, analog layout optimization, pitch layout, and assisting in the research and development for next generation products. LICENSED ACUPUNCTURIST -California and Nationally Certified Challen helps people with their health issues by using non-pharmaceutical modalities, nutrition and dietary guidance. BIBLE STUDY LEADER Challen is a volunteer Group Leader for Bible Study Fellowship International (BSF), discovering and worshipping God and our Lord and Savior Jesus Christ while promoting the study and practical use of the Word of God and its ability to clarify the daily and eternal issues of life.

Experience

1. Sr Staff Ic Layout Engineer

   Quantum-Si

   Dec 2021 — Present · US

   The best group of mature chip design engineers (from the VP, Manager, Pixel and Design Engineers to Layout) I\'ve experienced in my career as a Layout Designer. Each member of the small team worked remotely and was responsible for substantial amount of development and completion of each project. Every member is highly motivated, highly collaborative, self-directed, responsible, and open which contributed to a kind environment. I worked primarily with the CMOS team requiring analog, mixed signal, high voltage and mixed-power supply layouts for sensitive Imaging process. Responsibilities also included research and development of next generation layout design of new circuits and larger scale chip planning. Also involved with the periphery of Pixel Array on sensor side of the BSI chip.

Education

• Five Branches Institute College of Traditional Chinese Medicine

  Master of Traditional Chinese Medicine, Traditional Chinese Medicine and Chinese Herbology

  2004 — 2007

• Institute for Business and Technology

  IC Mask Design Certification, IC Mask Design, 4.0

  1989 — 1989

• Palo Alto High School

  High School Diploma, Automobile/Automotive Mechanics Technology/Technician - Mechanical Drafting

  1976 — 1980

• Foothill College

  Biology/Biological Sciences, General

  1992 — 2004

• United States Navy

  Technical, Advanced Electronics and Sonar Operations

  1980 — 1986