Challagolla Murali Krishna
Staff engineer at Qualcomm
- Role
- Staff Design Engineer at 高通
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Challagolla Murali Krishna
Physical Design Engineer with expertise- In Logic Synthesis, Physical Synthesis, Place and Route, STA (timing signoff), Physical Design Verification (DRC & LVS), Formal Verification, IR Drop Analysis and Low Power Implementation- Worked on Flat/hierarchical from RTL to GDSII with has hands on RTL compiler/DC Lec Conformal, Innovus/ICC2, tempus, redhawk, memory compiler- Has good understanding on timing concepts and ability on TCL/PERL scripting.
Experience
Staff Design Engineer
Nov 2021 — Present
Education
COEP Technological University
Master of Technology (MTech)
Sir CRR College of Engg
Bachelor of Technology (BTech), Electronics and Communication Engg
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