Challa Kowshik
Analog Design Engineer
- Role
- Sr Silicon Design Engineer at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Challa Kowshik
Started career with training at VEDA IIT in analog design. Worked for Synopsys ODC from Soctronics/Invecas. Working on PLL blocks in High Speed SERDES for lower nm tech nodes. Hands on experience on design of Clock dividers, Prescaler, Charge pump.
Experience
Sr Silicon Design Engineer
Jun 2024 — Present · Hyderabad, IN
Education
Indian Institute of Technology, Roorkee
Master of Technology - MTech, VLSI for Working Professionals
2027
JNTUK-UCEV
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2014 — 2018
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.