Chaitra Ajjagola Siddeshwarappa
Senior Asic Design Engineer @高通
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WORK HISTORY
Senior Asic Design Engineer @高通
San Diego, CA, US
RTL design Engineer in Video hardware team
EDUCATION
Siddaganga Institute of Technology (SIT), Tumkur
Bachelor of Engineering, electronics and communication
Arizona State University
Master of Science - MS, Electrical and Electronics Engineering
Sri Aurobindo Pre university, shimoga
Pre university, PCMB
ABOUT CHAITRA AJJAGOLA SIDDESHWARAPPA
Ms in Electrical Engineering from Arizona State University. Currently working as RTL design engineer in Qualcomm Video Hardware DE team. Skills:Tools: Cadence spectre, Cadence virtuoso, Cadence Innovus, smarTest, Ninja, Vtran pattern conversion tool, RTL synthesis, APRProgramming languages: C, Verilog, Python scripting, System Verilog, TCL, Hspice, Verilog Operating systems : Linux and windows
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