Chaithanya Nayak
Microarchitect and Logic Designer @Intel
Santa Clara, CA, US
EMAILS
MOBILE NUMBERS
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WORK HISTORY
Jun 2010 — Present
Microarchitect and Logic Designer @Intel
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SKILLS
Static Timing AnalysisC++Parallel ProgrammingProcessorsLow Power DesignVideo ProcessingPerlRtl DesignValidationLinuxDftVerilogCComputer Architecture
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