Krishna Chaitanya Kurmala
Engineer, Sr Staff/Mgr at Qualcomm
- Role
- Engineer, Sr Staff Mgr at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Krishna Chaitanya Kurmala
16+ years of experience in VLSI Industry. Played role in RTL Design, FPGA Emulation/Prototyping and Validation.• Currently Leading a Peripheral SOC and Core Emulation Team which deals with High Speed and Low Speed Peripherals Emulation/o The Peripherals Emulation Team is responsible for prototyping Peripherals across all the MSMs, MDMs and IOTs. Understanding the Architecture of Peripherals across projects. Planning a prototyping solution to each peripheral. Modifying ASIC RTL as per FPGA specs. Working with SW team to understand their requirements for each peripheral in terms of GPIO connections and several other link speeds needed by them for each protocol. Generating netlists using synplicity tool. Modifying the QBuild TCL(ZEBU based TCL) which is used to generate a Build which will be loaded to Emulation platfrom called RUMI ( ZEBU equivalent). Validating the prototyped solution. Works Closely with Software, Verification and other teams to close Different Kinds of issues Responsible for Debugging activities while Validating in Pre-silicon. Lead emulation/prototyping efforts for 2 SoCs and 1 IOT resulting in successful bring up on Silicon.Part of 10+ successful Tape Outs of SoCs targeted for mobile platform and 2+ IOTs targeted for Automotive/TV market.Expertise in debugging issues.Expertise in pre-silicon validation of IPs/SOCs/ASICs on FPGA.Hands on experience on Xilinx FPGAs.Worked on the entire FPGA prototyping flow which includes:Design partitioning, Area estimation, Synthesis,Area and Logic optimization, PnR,Timing Closure,On Chip debugging using Chipscope and other debugging tools, Bring Up of the FPGA platformWorked on Xilinx custom FPGA boards(HAPS Boards) as well as range of in-house Emulation Platforms having close to 100 FPGAsWorked on RTL IP designs for SDH/SONET based platforms.
Experience
Engineer, Sr Staff Mgr
Jul 2012 — Present · Bangalore, IN
Education
Indian Institute of Technology, Guwahati
M.Tech
Skills
- Fpga
- Tcl
- Debugging
- Modelsim
- Static Timing Analysis
- Rtl Design
- Vhdl
- C
- Vlsi
- Verilog
- Digital Design
- Xilinx
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