Chaitanya Roy Buddhavaram
Asic Design & Verification - Trainee @Maven Silicon
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WORK HISTORY
Asic Design & Verification - Trainee @Maven Silicon
I am currently enrolled in the Advanced ASIC Design and Verification course, a program specialising in Front-end VLSI Design and Verification. I am combining my Electronics background with the Artificial Intelligence experience from my internships to master complete chip design flow.Core Focus Areas-RTL Design: Writing clean and synthesizable Verilog code and designing robust FSMs and Control logic-Verification: Verification methodologies using System Verilog and UVM-Automation: Perl scripting for automating industry standard EDA tools like Synopsys, Cadence, Xilinx & Aldec
EDUCATION
Muffakham Jah College of Engineering & Technology
Bachelor of Engineering - BE, Electrical, Electronics and Instrumentation Engineering
Ernst-Abbe-Hochschule Jena
Master's degree, Scientific Instrumentation
ABOUT CHAITANYA ROY BUDDHAVARAM
I am an aspiring Electronics engineer with a strong foundation in digital logic and a passion for hardware architecture. Currently, I am undergoing intensive training at Maven Silicon, specialising in Application Specific Integrated Circuit (ASIC) Design and Verification.My Journey: During my tenure as a Computer Vision working student and Intern, I gained strong proficiency and hands-on experience in Python and algorithmic logic. At the same time, it also sparked a deep curiosity: How does a chip in Nvidia Orin execute highly complex computer vision algorithms so efficiently?The question drove me back to my roots. All thanks to the German education system for letting me learn what I have wished for. Thus, I combine an Electronics & Instrumentation background with professional coding experience in computer vision using Python.This hybrid skillset allows me to approach the verification problem with a developer\'s mindset, too.Current Status- Training: Advanced ASIC Design & Verification at Maven Silicon- Skills: Verilog, SystemVerilog, UVM, Digital Logic, Python, Perl- Goal: To pursue my career in the VSLI field and secure entry level role in RTL Design or Verification.Open to entry level oppurtunities in RTL Design and Verification, and as an FPGA design and verification.
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