Cassie Y.
CPU Microarchitect/RTL Engineer
- Role
- Cpu Microarchitect Rtl Engineer at Apple
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
About Cassie Y.
CPU microarchitect/RTL engineer with extensive and in-depth experience across different…
Experience
Cpu Microarchitect Rtl Engineer
Feb 2016 — Present · San Francisco, CA, US
Define and design CPU backend Load-Store-Unit mircro-architecture and other functional units inside custom Apple A-series processors.
Education
University of Michigan
BS
2012 — 2014
Shanghai Jiao Tong University
B.S.E Electric
2010 — 2014
University of Michigan
Master's degree
2014 — 2015
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