Carol L.
- Role
- Manager for Standard Cell Library Team for 7nm, 10nm and 14nm Libraries at Intel
- Location
- Rancho Santa Fe, CA, US
- LinkedIn followers
- 500 followers
About Carol L.
Professional Experience: MSEE with 10+ years VLSI/ASIC design experience in Intel.…
Experience
Manager for Standard Cell Library Team for 7nm, 10nm and 14nm Libraries
Jan 2016 — Present
Logic lead for the team. Defined and wrote software to generate and validate logic collateral (UDP verilog, behavioral verilog bmod, ATPG, UDFM) for the library using SiliconSmart/Conformal/ESP/Mentor. Ensured customers are successful using library collaterals for FEV, GLS, UPF, and test pattern generation. Interacted with Synopsys SiliconSmart AE to enhance their verilog generation software. • Designed clock cells circuit on 10nm and 14nm process.
Skills
- Logic Synthesis
- Verilog
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