Carlos Tadeo Ortega Otero

Senior Member Research Staff @IBM

Los Angeles, CA, US
MOBILE NUMBERS
+16•••••••44

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WORK HISTORY

Jun 2022 — Present

Senior Member Research Staff @IBM

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Santa Monica, CA, US

EDUCATION

1998 — 2001

Instituto Juventud del Estado de Mexico (IJEM)

High School diploma

2007 — 2014

Cornell University

Doctor of Philosophy (Ph.D.), Computer Engineering

2001 — 2006

Tecnológico de Monterrey

Bachelor of Science (B.S.), Computer Engineering

2006 — 2012

Cornell University

Master's degree, Computer Engineering

SKILLS

Software EngineeringIntegrated Circuit DesignGitPerlUnixAlgorithmsCProgrammingVerilogLinuxDatabasesSimulationsOperating SystemsVlsiCircuit DesignMatlabC++JavascriptSoftware DevelopmentPythonLatexHtmlJavaResearchComputer ArchitectureComputer Science

ABOUT CARLOS TADEO ORTEGA OTERO

I currently work as a Research Scientist in the Brain-Inspired Computing group at IBM Research. My research interests lie at the intersection of ultra-low energy design, event-driven computation, and novel computing architectures.Before joining IBM, I worked as an R&D Engineer at St. Jude Medical in the cardiology division. At St. Jude, he developed first-of-its-kind prototypes for MEMS based implantable sensors to detect blood pressure on patients with heart disease.I have designed and fabricated over 9 complex integrated circuits (ICs) that range from a general purpose MCU to an FPGA. I also provided assistance to build True North chip designed by IBM.I get involved in all parts of the design process, from inception to microarchitecture to physical circuit design, as well as PCB and assembly design. I am productivity oriented, I use scripts, simulators and tools to increase productivity and deliver functional chips as fast as possible. All the ICs that I\'ve worked on were functional on first-silicon.My latest MCU testchip (ULSNAP) uses only 47pJ and runs at 93Mhz, it is in the pareto-optimal curve of the Energy-Performance curve. Our FPGAs range from 340Mhz in 130nm to 800Mhz in 65nm technologies.In addition to my practical experience, I also analyze the tools and methodologies to understand and develop asynchronous circuits- I developed complex techniques to allow power gating in the context of asynchronous circuits- I have developed and evaluated techniques for automatic full-custom quality layout- I have developed and evaluated techniques for creation of isomorphic and obfuscated layout.

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