Bupendra B.

Principal Applications Engineer @Cadence

Simulation, Synthesis, Formal Verification, Jasper, High Level Synthesis, CtoSilicon, SystemC, Verilog, SystemVerilog, SystemVerilog Assertions, VHDL, C/C++, Stratus HLS, Incisive Unified Simulator, Incisive Enterprise Simulator, Genus Synthesis Solution, Innovus Implementation System, Conformal Low Power, Confomal LEC, Conformal ECO, Conformal Constraint Designer, Linting, Static Timing Analysis (STA), ASICs, SoCs, EDA CAD, Clock Tree Synthesis, Timing Closure, Power Analysis, RTL Compiler, Jasper, Xcelium, Joules RTL Power Solution, Cadence Palladium emulation hardware for Dynamic Power Analysis using RTL Compiler Power EstimationDemonstrated experience in successful first time correct silicon tape-outs of complex chipsKnowledge and understanding of place and route LEF/DEF design data files - physical design concepts and constraints such as floor-planning, placement, congestion, and setup/hold timing closure with experience of using First Encounter, SoC Encounter, Encounter Digital Implementation, Innovus Implementation SystemExperience in interacting and collaborating with silicon foundries and other external vendorsPre-salesPost-sales