Brijesh Patel

About Brijesh Patel

Hardware engineering leader driving the design and delivery of high-performance and low-latency networking switches that power hyperscale AI data centers. Responsible for end-to-end hardware design, skilled in solving complex design problems, and a key contributor across multiple projects while leading multi-functional teams.> Over 15 years of specialized experience in designing cutting-edge products and high-performance network switches for hyperscaler AI data centers.> Deep expertise in high-speed board design (112G/224G) based on Broadcom, Qualcomm, Intel, AMD, TI, and Freescale processors.> Proven track record of translating design concepts into physical products using specialized knowledge and advanced methodology of hardware design.> Extensive hands-on experience in product architecture, feasibility analysis, electronics circuit simulation, electronic component selection, and Schematic design.> Strong experience in PCB LAYOUT (46+ layers) Design/Review.> Expertise in Signal Integrity optimization for 112G/224G SerDes, via structure design, and crosstalk analysis to comply with requirements.> Hands-on experience in Power Integrity analysis, including PDN modeling and decoupling capacitor optimization.> Proficient in Verilog and SystemVerilog coding for FPGA and CPLD implementation.> Hands-on experience in hardware bring-up, debugging, engineering design validation (EDVT), and power and performance analysis using advanced hardware lab instruments.> Solid understanding of design for functionality, manufacturability, and testability.> Experience supporting EMI/EMC testing, FCC & CE certification, and RoHS & REACH compliance activites.

Experience

1. Sr Hardware Design Engineer

   Arista Networks

   Aug 2022 — Present · Santa Clara, CA, US

   Designed a next-generation ultra-high-speed 204.8 Tbps network switch for AI hyperscale data centers, delivering mega-scale bandwidth to GPU clusters for demanding workloads.Serving as Lead Senior Engineer, defining overall product architecture and technical specifications.Designing a high-density 46-layer PCB design, and schematic development using Cadence tools. Expert in 224G PAM4 Signal and Power Integrity analysis, Verilog RTL for FPGA/CPLD, and firmware for power/clock devices. Led cross-functional teams, executed hardware bring-up/debug, authored hardware specification and test documentation,

Education

• Ganpat University

  B.Tech, Electronics and Communications Engineering

  2006 — 2010

• San José State University

  Master's degree, Electrical and Electronics Engineering

Skills

• Linux
• High Speed Interfaces
• Uart
• Layout Tools
• Vhdl
• Ni Labview
• Embedded C
• Ddr3
• Oscilloscope
• Pads Layout
• Universal Asynchronous Receiver/Transmitter (Uart)
• Network Simulator
• Embedded Systems
• Verilog
• Hardware Bring-Up
• Ethernet
• Dmms
• Cadence Schematic Capture