Brent Lui

About Brent Lui

CPU & ASIC professional.20 years in ASIC,CPU chip design and design verification area. Strong experiences in all aspects of ASIC and CPU design verification & design including design verification, function verification,architecture verification,CPU pipeline design verification,test plan,test bench,develop testcases, assembly tests,Compatibility tests, Random tests,gate level simulation, regression,coverage,RTL debug, RTL design,RTL synthesis,Timing verification,Metal fix,Post-layout debug,prime time,Power anlysis, Test vector generation,LEC with cadence Conformal.Strong experience in Superscaler & superpipe ARM CPU design verification,DDR design verification & complex ASIC design(G-bit Ethernet.),CPU subsystem design.Strong experience in ASIC design flow.Experience design/design verification in different CPU architecture(ARM,x86,MIPS).Experience several complex Networking ASIC design(G-bit ethernet,MCNS cable modem client,Media gateway,TCAM) through complete development cycles.

Experience

1. Staff Logic Verification Engineer,logic Design Engineer

   Marvell Technology

   Jun 2005 — Present

   ARM V7 superscalable & superpipeline quad-core CPU logic/architecture design verification.Worked on module level and full chip design verification. DDR controller ASIC design verification.ARM CPU full chip gate level simulation verification

Education

• Syracuse University

  MS, computer engineering

  1989 — 1991

• National Chiao Tung University

  BS, electronic engineering

  1981 — 1985

Skills

• Arm Pipeline Architecture Verification
• Microarchitecture
• Uvm
• Computer Architecture
• Rtl Coding
• Logic Design
• Ddr3,Ddr2,Lpddr Controller Design Verification
• System Verilog
• Rtl Design
• Axi Bus
• Ncsim
• Communication Chip Logic Design
• Logic Synthesis
• Timing
• Ddr Design Verification
• Arm Asic Logic Verification
• Asic
• Systemverilog
• Arm Cpu Logic and Architecture Verification
• Amba Ahb
• Low-Power Design
• Arm
• Verilog
• Processors
• Superscalable & Superpipeline M-Core Arm Cpu
• Debugging
• G Bit Ethernet Switch
• Ethernet
• Semiconductors
• Timing Closure
• X86
• Modelsim
• Soc
• Arm Assembly Language
• Static Timing Analysis
• Synopsys Tools
• Random Arm Assembly Tests Generator
• Cadence
• Integrated Circuit Design
• Microprocessors