Bo L.
Principal Engineer of ASIC design and verification at Averlogic Technologies Inc.
- Role
- Principal Engineer, Asic Design and Verification at Averlogic Technologies Corp
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Bo L.
More than 10 years digital ASIC design and verification experience7+ Video/image processing related, mixed-signal or SoC chips successful tape-out· Knowledge of ASIC backend design flow and analog IC design flow· System design background: hardware, PCB, embedded system firmware· Verilog HDL, VHDL, PLI, Tcl, Perl, Python, UNIX Shell language· SystemVerilog, UVM/OVM· C/C++, Assembly· Image processing, DSP, Matlab, Computer Vision· Machine Learning, Image Recognition, TensorFlow· ModelSim, NC Verilog, LEC, SoC Encounter, Virtuoso, Incentia DesignCraft· Altera/Xilinx FPGA, QuartusII, ISE/Vivado, ChipScope, Synplify, OrCAD, PowerPCB· Analog & Digital TV system architecture, LCD monitor, LCD TV· Video/image processing and compression, H.264· LPDDR/DDR DRAM controller, AMBA, AHB/AXI, Wi-Fi 802.11
Experience
Principal Engineer, Asic Design and Verification
Jul 2007 — Present · San Jose, CA, US
Education
San José State University
MS, EE
2006 — 2007
Udacity
Nanodegree, Self-Driving Car
2017
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