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Brijesh Vaghasiya

Engineer at Google

Role
Silicon Design Verification Engineer at Google
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

Experience

  1. Silicon Design Verification Engineer

    Google

    Jul 2022 — Present

Education

  • Dharmsinh Desai University

    Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

    2008 — 2012

Skills

  • Tcl
  • Verilog
  • Vhdl
  • C
  • Perl
  • C++ Language
  • Open Verification Methodology
  • Vlsi
  • Algorithms
  • C++
  • Linux
  • Modelsim
  • Functional Verification
  • Asic
  • Uvm
  • Pcie
  • Systemverilog
  • Sata

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Brijesh Vaghasiya — Silicon Design Verification Engineer at Google in Bengaluru, KA, IN | Unifers