Biswa Ranjan Panda

About Biswa Ranjan Panda

11+ years of experience in High-Speed SerDes and Power management IC Layout Design.• Experienced in 18Gbps transceiver data link layout, clock distribution blocks, Ring PLL, 16Gbps MIPI DSI SERDES IP\'s and EFUSE, DUAL EFUSE, Switching Regulator power management product. • Developing in-depth knowledge in Serializer, TX driver, De-serializer, Equalizer, Rx termination, Phase Interpolator, Ring PLL, Clock Divider, DCC etc. to ensure drawing an efficient layout.• Sound knowledge of EDA tools such as Virtuoso Layout Editor, Calibre, Innovus, Totem, Redhawk, Assura, ParagonX, magwell, VotusFI, Innovous basics.• Worked on various process nodes such as 4nm, 5nm, 7nm, 10nm (SEC), 4ff, 7ff, 10ff, 14ff, 16ff (TSMC), 350nm (Magnachip), 180nm, 90nm (GF).• Quick adaptation to newer tech nodes and PDKs, new collaterals and new sign-off checks. Script and Flow related layout initiatives to reduce tedious manual efforts and improve quality. • Dynamic in teamwork, taking up initiatives, guiding teams & managing workforce to optimize daily output.• Contributing to the SOC’s Power, Performance, Area (PPA) to deliver the best in the industry Processors. Interacting with different teams such as Design, Char, PD, SOC, PDN, PV, Package in different stages of the project to ensure the industry’s best IP quality. • Able to motivate and lead the layout team for developing high-speed SerDes layout.

Experience

1. Senior Staff Layout Engineer

   高通

   Dec 2025 — Present

Education

• B.O.S.E SC&VT

  B.P.U.T; DIPLOMA, ECE

  2005 — 2008

• NIST University

  B.TECH, ECE

  2008 — 2011

Skills

• Cmos
• Vhdl
• Verilog
• Physical Verification
• Internet
• Vlsi
• Tcl
• Analog
• Perl Script
• Lvs
• Cadence
• Soc
• Drc
• Perl
• Cadence Virtuoso
• Physical Design