Lokesh Bingi

About Lokesh Bingi

I am a VLSI Physical Design Trainee with hands-on training in the ASIC physical design flow, including floorplanning, placement, clock tree synthesis (CTS), routing, and static timing analysis (STA) using industry-standard EDA tools.My technical exposure includes PnR methodologies, timing closure, constraint handling (SDC), physical optimization, congestion analysis, and power/performance trade-offs. I have a working understanding of PD signoff basics, timing analysis with PrimeTime, and physical design best practices in advanced technology nodes.I am proficient in Synopsys Physical Design tools, with foundational knowledge of ICC2, PrimeTime, and Linux environment, and familiarity with ASIC design concepts, clocking strategies, and ECO flow.I am actively seeking entry-level / trainee opportunities in VLSI Physical Design, where I can contribute to high-quality silicon implementation, strengthen my technical skills, and grow as a Physical Design Engineer.

Experience

1. Trainee

   ChipEdge

   Oct 2025 — Present · Bengaluru, IN

Education

• Marri Educational Society's Marri Laxman Reddy Institute of Technology and Management

  Btech

  2021