Bin Wang

About Bin Wang

10 Years of experience in low power high speed digital circuit design from RTL to GDS…

Experience

1. Senior Asic Design Engineer

   NVIDIA

   Jan 2019 — Present

   Design and Deliver high speed ARM state-of-art CPU in 10nm Pre-Layout: Physical-aware logic synthesis from RTL to gate level netlist: I/O budgeting, critical path optimization(group & weight customization), low power implementation, layout floor-planning, NDR for interconnects, custom region for sequential elements Apply detailed SPICE simulations and timing analysis for new architectures with wire model Post-layout: Block-level STA using PrimeTime Generate both manual and automatic ecos for timing closure Formal Verification for netlist with ecos Block-level power characterization using PTPX Clean-up of back-end analysis: IR Drop, SigEM, SI, etc.

Skills

• C++
• Place & Route
• Formal Verification
• Eda
• Perl
• Circuit Design
• Timing Closure
• Primetime
• Cadence Virtuoso
• Semiconductors
• Perl, Tcl
• Very-Large-Scale Integration (Vlsi)
• Sta Timing Closure
• Static Timing Analysis
• Custom Sram Circuit Design
• Linux
• C
• Simulations
• Physical Design
• Low-Power Design
• Physical Verification
• Matlab
• Integrated Circuits (Ic)
• Cadence Virtuoso Layout Editor
• Spice
• Verilog
• Rtl Design
• Cmos Design
• Tcl