Bibin Paul

About Bibin Paul

Senior Principal-level High-Speed Serial Interface and SoC Design Engineer with 14.5+ years of experience delivering first-pass silicon across complex mixed-signal SoCs and high-speed interfaces. Strong expertise in architecture, custom silicon, PCS design, RTL implementation, and silicon execution for multi-protocol PHYs and custom retimer solutions.End-to-end execution ownership spanning specification, micro-architecture, RTL design, block-level DV, top-level integration, lint/CDC closure, SDC development, STA reviews, GLS debug, ECO resolution, FPGA prototyping, and post-silicon validation. Known for strong debug methodology, observability-driven design, and predictable execution on first silicon.Recognized technical leader with experience in mentoring engineers, task planning, delegation, and automation, enabling high-quality and on-time delivery across cross-functional teams.Protocols & Interfaces: USB 3.1 (Gen1/Gen2), DisplayPort, PIPE 4.3/6.2, AMBA AXI/AHB/APB, I2CDomains: High-Speed Serial, SerDes, PHY, PCS, Retimers, Mixed-Signal SoCs

Experience

1. Senior Principal Engineer

   NXP Semiconductors

   Nov 2022 — Present · Bengaluru, IN

   As part of the R&D team, specialized in architecture, design, and implementation of high-speed serial interfaces, with strong ownership of PCS architectures for multi-protocol PHYs and custom USB retimer solutions.Led TX and RX datapath architecture and RTL design for ~10 Gbps interfaces, including elastic buffers, aligners, gearboxes, PIPE (4.3/6.2) interfaces, encoding/decoding schemes (128b/132b, 8b/10b), scramblers, and PRBS generator/checker–based BIST logic. Owned clock/reset architecture and datapath robustness across Gen1/Gen2 operation.Designed and implemented control paths for multi-lane SerDes supporting USB and DisplayPort, including TX/RX analog controllers, CDR control logic, calibration sequencers, message-bus operations, and USB retimer–PHY interactions. Developed controllers and calibration algorithms for mixed-signal blocks such as high-speed clock recovery circuits (~11 Gbps) and PLLs, supporting integration and bring-up.Architected and delivered a protocol-agnostic high-speed framing subsystem, including TX/RX framing logic, frame structure definitions, bandwidth optimization, and clean interfacing with the USB retimer and PHY subsystems.Drove subsystem specifications and micro-architecture, RTL implementation, block-level DV, top-level integration, lint/CDC closure, SDC development, STA reviews, GLS debug, and ECO resolution in close collaboration with PD, DV, and validation teams. Designed debug and observability logic to accelerate silicon validation and FPGA prototyping, enabling efficient root-cause analysis during bring-up.Actively improved execution efficiency through automation and provided technical leadership and mentorship, including task definition, delegation, design reviews, and progress tracking for junior engineers. Delivered consistent first-pass silicon success across all assigned designs.Protocols & Interfaces: USB 3.1 (Gen1/Gen2), DisplayPort, PIPE 4.3/6.2, AHB, APB, I2C

Education

• Indian Institute of Technology, Madras

  Master of Technology - MTech, Integrated Circuits and Systems

• St Peters Senior Secondary School, Kadayiruppu

  AICBSE, High School/Secondary Diploma Programs

  1994 — 2007

• Government Rajiv Gandhi Institute of Technology Kottayam

  Bachelor of Technology (BTech), Electronics and Communications Engineering

  2007 — 2011

Skills

• Automatic Test Pattern Generation (Atpg)
• Tcl
• Perl
• Physical Design
• Embedded Systems
• Embedded C
• Functional Verification
• Verilog
• Cdc Analysis
• Pcie
• Fpga
• Soc
• Asic
• Rtl Coding
• Control Path Design
• Rtl Design
• Open Verification Methodology
• Timing Closure
• Logic Design
• Rtl Verification
• Amba Axi
• Static Timing Analysis
• Digital Electronics
• High Level Design Requirement Gathering & Presentations
• Pci Express
• Vhdl
• Integrated Circuit Design
• Microprocessors
• Lint
• Sdc Development
• Modelsim
• Xilinx Ise
• Formal Verification
• Vlsi
• Hardware Architecture
• Cadence Virtuoso
• Ncsim
• Microarchitecture
• Xilinx
• Systemverilog