Bibin N Biji

About Bibin N Biji

I am a Senior Physical Design Engineer with 4+ years of experience in block-level RTL-to-GDSII implementation, specializing in MCMM timing closure, CTS optimization, congestion mitigation, and ECO convergence across advanced ASIC flows.My expertise spans complete physical implementation ownership — from floorplanning and macro clustering to post-route optimization and signoff readiness. I have driven timing closure across multiple PVT corners and functional modes, consistently balancing performance, power, and routability trade-offs. Core Strengths• Block-level floorplanning & congestion-aware placement• MCMM setup/hold closure across PVT corners• ccopt-based CTS skew & latency tuning• Post-route ECO implementation & incremental routing• Useful skew application for critical path recovery• PDN awareness & IR drop fundamentals• Timing signoff exposure (Tempus / PrimeTime) Tools & AutomationCadence Innovus (Primary), ICC2 exposure, Tempus, PrimeTime, CalibreTCL & Python scripting for QoR extraction and automation What Differentiates MeMy background in RTL and verification enables stronger cross-functional debugging, faster implementation convergence, and architecture-aware timing optimization.I am currently open to challenging Physical Design / Implementation roles where I can contribute to high-performance SoC programs and advanced node design methodologies. Open to BangaloreOpen to collaboration, ASIC consulting, and full-time opportunities.

Experience

1. Vlsi Engineer

   Yarok14 Technologies

   Jan 2022 — Present · Kochi, IN

   ASIC RTL to GDSII Design

Education

• Cochin University of Science and Technology

  Bachelor of Technology - BTech

• Kerala Board of Public Examination (KBPE)

  HSC and SSLC