Bhuvaneswari Putluru
Design Verification Engineer @BITSILICA
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WORK HISTORY
Design Verification Engineer @BITSILICA
Hyderabad, IN
EDUCATION
Visvesvaraya National Institute of Technology
Master of Technology - MTech, VLSI
G Narayanamma Institute of Technology and Sciences
B.tech, Electrical, Electronics and Communications Engineering
Narayana Junior College - India
High School Diploma, Maths,Physics,Chemistry
ABOUT BHUVANESWARI PUTLURU
Areas of interest: RTL Design,Physical Design,STA,Verification,Analog Circuit Design,Layout Design,ASIC Design,DFT,Memories and SemiconductorGood Knowledge on RTL(Verilog,VHDL),Physical Design flow,STA,CMOS technology basics. In-depth Knowledge on ASIC flow,FPGA and Verification Methodologies like DRC,LVSHands on experience on CAD Tools:Design Complier,DFT,Innovus,Genus,DRC,LVS,Cadence Virtuoso Layout Editor,Sentaraus TCAD,Nano VidesWorked for Tapeout of 802.15.4 MAC Protocol SCL 180nm Technology under SMDP-C2SD a Govt. program to develop VLSI design in our Country.60 Academic Institutions are part of this program.Thorough Knowledge on IC Design with HDL,CMOS Digital VLSI Design,Analog IC Design,Design for Testability Yield and Reliability which are my Course works in M.TechStrengths:Hardworker,eager to learn,Self Motivated,Being Responsible
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