Bhavya Sri M

“Design Verification Engineer | UVM Expert | Verified DMA, AXI/APB IPs”

Role
Design Verification Engineer at Intel
Location
Bellevue, WA, US
LinkedIn followers
500 followers

About Bhavya Sri M

ASIC/SoC Design Verification Engineer specializing in SystemVerilog and UVM-based verification for complex digital and processor-based designs. Experienced in developing scalable UVM testbenches, constrained-random stimulus, SystemVerilog Assertions (SVA), and functional coverage models to validate RTL functionality and improve verification completeness.Hands-on experience verifying processor architectures, including pipeline behavior, instruction execution, and memory/cache interactions. Skilled in debugging RTL issues, identifying corner-case scenarios, and improving design quality through coverage-driven verification methodologies.Proficient in SystemVerilog, UVM, Verilog, and Python automation with experience using simulation tools such as Synopsys VCS and Cadence Xcelium. Strong foundation in computer architecture and SoC verification workflows, focused on delivering reliable and high-quality silicon.

Experience

  1. Design Verification Engineer

    Intel

    Jan 2023 — Present

    Architected and owned end-to-end UVM-based verification environments in SystemVerilog for heterogeneous SoCs, covering multi-core CPU/GPU subsystems, cache coherence (ACE/CHI/MESI), CDC/RDC, and assertion-based verification (SVA) to ensure protocol correctness and robust design validation.• Led verification of high-speed interfaces and memory subsystems including PCIe Gen5/6, CXL, DDR5/LPDDR, and SerDes PHY, leveraging coverage-driven verification, IBIS-AMI modeling, and advanced debug techniques to resolve timing, signal integrity, and interoperability issues.• Drove scalable verification strategies and infrastructure, integrating emulation/prototyping (Palladium, Veloce, FPGA), regression automation, and functional coverage closure to accelerate bug detection, improve verification efficiency, and support pre/post-silicon validation.

Education

  • University of Cincinnati

    Masters of engineering, Electrical and Electronics Engineering

  • Velagapudi Ramakrishna Siddhartha Engineering College

    Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

Find verified contacts for anyone on LinkedIn

Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.

Free plan included · No credit card required

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.

Bhavya Sri M — Design Verification Engineer at Intel in Bellevue, WA, US | Unifers