Bhavna Muley

WORK HISTORY

EDUCATION

ABOUT BHAVNA MULEY

Diving deep into the mesmerizing realm of 1\'s and 0\'s, I\'ve fostered a passion for Digital Electronics, embracing a positive logic in both my endeavors and outlook. With an ardent fascination for the VLSI industry, I\'m driven to contribute my honed skills and knowledge towards excelling in Design and Verification. Eager to make my mark in this dynamic field, I aspire to be a catalyst for innovation and progress.Here is a sneak peak of what I know:>HDL: Verilog>HVL: SystemVerilog>Verification Methodologies: Constraint Random Coverage Driven Verification, Assertion Based Verification - SVA>TB Methodology: UVM>Protocols: AXI, AHB, UART, I2C, SPI>EDA Tool: Mentor Graphics - Questasim and Xlinix - ISE, Xilinx -Vivado, VCS, Modelsim, Quartus-Prime, Cadence Virtuoso, TSpice, HSpice>Domain: ASIC/FPGA front-end Design and Verification >Programming Languages: C [Datatype | Array | Pointers | Memory Allocation | List |Queues and stacks | Data structure, Functions] C++( Good knowledge of OOPs concept, Class, Inheritance, Polymorphism )>Operating System: Linux>Scripting Languages: Perl Scripting>Core Skills: RTL Coding using Synthesizable constructs of Verilog, FSM based design, Simulation, CMOS Fundamentals, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis, Assertion Based Verification using SystemVerilog Assertions, SRAM Design, Low Power Circuit Design, CNTFET Circuit Design, Lower Technology nodes.Hands-On Experience:>Router 1X3: Design using Verilog and Verification using UVM>Dual Port RAM VerificationBehavioral Skills:>Interpersonal Communication >Collaborative>Organized>Critical Thinking