Bhavani Patil
Senior Engineer II - Validation | Ex AMD | RTL Design and Verification (SoC/FPGA)
- Role
- Senior Engineer Ii - Validation at Microchip Technology Inc.
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Bhavani Patil
Overall 7+ years of experience in FPGA Design and Verification ->Hands-on…
Experience
Senior Engineer Ii - Validation
Sep 2024 — Present · Hyderabad, IN
Education
VTU regional center gulbarga
Master of Technology (M.Tech.)
2014 — 2016
Skills
- Windows
- C
- Programming
- Microcontrollers
- Unified Modeling Language (Uml)
- Microsoft Office
- Electronics
- Matlab
- Linux
- Vhdl
- Simulations
- Verilog
- Research
- Embedded Systems
- Very-Large-Scale Integration (Vlsi)
- C++
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