Apurv Bhatt
Senior Manager, at AMD | Silicon Verification | SoC & IP Methodology | Formal & AI/ML
- Role
- Sr Manager Silicon Design Engineering at AMD
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Apurv Bhatt
As Individual Contributor- Hands on experience of HVLs like systemverilog and standard methodologies like UVM- Exposure to ARM microarchitecture- Hands on experience with IO protocols like SATA and PCIe. Worked on Networking protocols like OTN- Familiarity with scripting languages like PERL. As Verification Lead- Leadership experience in different semiconductor companies in India, USA, and Canada - Proven track record of delivering bug free RTL designs for multiple tapeouts- Guiding and mentoring junior team members for verification work As Verification manager- 5+ years of experience in managing small to large teams across different geographies- Hands on experience with Long term resource planning and hiring- Managing the team across different geographies- Experience in coaching senior staff members for functional verification
Experience
Sr Manager Silicon Design Engineering
Sep 2025 — Present · Austin, TX, US
Education
Gies College of Business - University of Illinois Urbana-Champaign
Master of Business Administration - MBA
Gujarat University
Bachelor of Engineering - BE, Electronics And Communication, VLSI, ASIC
1999 — 2003
Skills
- Rtl Design
- Functional Verification
- Optical Network
- Otn
- Vlsi
- Fpga
- Asic
- C++
- Perl
- Open Verification Methodology
- Debugging
- Modelsim
- Uvm
- Systemverilog
- Sata
- C
- Verilog
- Soc
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