Bhasker Jakka

About Bhasker Jakka

With over 26 years of hands-on and leadership experience in ASIC/SoC development, I\'ve had the privilege of working at the intersection of cutting-edge silicon and transformative technology — from AI acceleration to enterprise storage to wireless communications. As Lead Silicon and Systems Engineer at Meta, I lead MTIA silicon development, validation, and release to production — bringing up and qualifying the chips that power AI experiences for billions of people worldwide. MTIA is Meta\'s family of homegrown AI accelerators, and a cornerstone of Meta\'s AI infrastructure strategy. The program has scaled across four successive generations — MTIA 300, 400, 450, and 500 — with hundreds of thousands of chips deployed in production data centers. Before Meta, as ASIC Director at Western Digital, I led SoC development for enterprise-class SSD controllers from architecture through silicon validation. My foundation spans IMEC and STMicroelectronics, where I designed wireless LAN ASICs, developed DSP algorithms, and managed cross-functional hardware engineering teams. What I bring to the table:• Silicon development, validation & production release of high-volume AI accelerator chips• Expertise across all major EDA tools and ASIC methodologies including SW/FW development for AI Accelerators• Patents and international conference publications• A track record of leading high-performing engineering teams in fast-moving environments I thrive where deep technical rigor meets execution excellence.

Experience

1. Lead Silicon and Systems Engineer

   Meta

   Nov 2018 — Present · San Francisco, CA, US

   SoC/ASIC Development • Host SW and Device FW development for pre-silicon (Emulation) and post-silicon functional validation• Comprehensive Performance measurements • Lead teams on strategy, development and execution

Education

• Indian Institute of Technology, Delhi

  Master of Technology, Electrical Engineering

  1997 — 1998

• University of Stuttgart

  Master of Engineering, Digital Signal Processing

  1998 — 1999

Skills

• Systemverilog
• Soc
• Integrated Circuit Design
• Verilog
• Physical Design
• Static Timing Analysis
• Hardware Architecture
• Ncsim
• Digital Signal Processors
• Ic
• Logic Synthesis
• Timing Closure
• Silicon Validation
• Vlsi
• Vhdl
• Fpga
• Asic
• Universal Verification Methodology (Uvm)
• Semiconductors
• Rtl Design