Bhargav Vijay
ASIC Physical Design Engineer at NVIDIA
- Role
- Asic Physical Design Engineer at NVIDIA
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Bhargav Vijay
M.S Electrical Engineering.CGPA: 3.89/4.Very passionate about semiconductor devices. Major projects pertaining to SRAM decoder, floorplanning tool, bipartiotioner and static timing analyzer tools. Technical Skills:Tools and Simulators: Cadence Virtuoso, Synopsys HSPICE, Cosmoscope, Synopsys VCS, Synopsys DVE Programming Languages: C, C++(STL), Cadence SKILL, PERL. HDL Languages: Verilog, SystemVerilog.Physical Verification Tools: Mentor Graphics Calibre (DRC, LVS, PEX).Verification Methodologies: UVM, CRV.
Experience
Asic Physical Design Engineer
Jun 2019 — Present · Santa Clara, CA, US
Advanced timing closure -Assisting in the synthesis of multiple blocks containing multivoltage and CDC\'s-Worked on timing analysis on 7nm technology using PRIMETIME-Assisted in bringup and post silicon activities, especially to verify the clock architecture and features
Education
University of Mumbai
Bachelor’s Degree, B.E Electronics
2011 — 2015
University of Minnesota
Master's degree, Electrical and Computer Engineering
2017 — 2019
Skills
- Microsoft Office
- Embedded Systems
- Vhdl
- Microsoft Word
- Sizer Software
- Matlab
- C++
- Microsoft Excel
- Powerpoint
- Computerised Numeric Control(Cnc)
- Java
- C
- Programming
- English
- Machine Tools
- Drives
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