Bhargavraj Patel
Cache Coherency | Out Of Order CPU | PCIE Ordering | ASIC Design Verification | Cadence Palladium | ARM Architecture
- Role
- Manager at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Bhargavraj Patel
Experienced professional with a demonstrated history of ASIC Verification at both unit and SOC level. Strong knowledge of Cache coherency, CPU micro architecture, PCIE Ordering, RTL design/verification, Performance verification and simulation acceleration. Skilled in System Verilog, UVM - constraint random, coverage driven verification, Cadence Palladium platform.
Experience
Manager
Aug 2018 — Present · Santa Clara, CA, US
Education
Northwestern University
Master's, Electrical and Computer Engineering
2011 — 2013
Dharmsinh Desai University
Bachelor of Engineering, Electronics and Communication
2005 — 2009
Skills
- Asic
- Macroeconomics
- Cadence Palladium
- C
- Programming
- Semiconductors
- C++
- Vmm
- Very-Large-Scale Integration (Vlsi)
- Soc
- Cache Coherency
- Algorithms
- Functional Verification
- Rtl Design
- System on a Chip (Soc)
- Systemverilog
- Uvm
- Vlsi
- Computer Architecture
- Linux
- Verilog
- Matlab
- Arm
- C/C++ Stl
- Integrated Circuit Design
- Microprocessors
- Perl
- Entrepreneurship
- Application-Specific Integrated Circuits (Asic)
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