Bhargavi Lukalapu
Physical Design Engineer | SoC Implementation & Low-Power Design | RTL-to-GDSII | Timing Closure & Signoff | Advanced Nodes (7nm–3nm) | EDA Tools: Innovus • ICC2 • PrimeTime
- Role
- Physical Design Engineer at Microchip Technology Inc.
- Location
- Chandler, AZ, US
- LinkedIn followers
- 500 followers
About Bhargavi Lukalapu
I’m a Physical Design Engineer with over 4 years of hands-on experience delivering…
Experience
Physical Design Engineer
Aug 2024 — Present · AZ, US
Worked on SoC floorplanning and block-level physical integration for microcontroller-based SoC designs with both analog and digital domains, collaborating with architecture and RTL teams to define physical constraints early in the design phase-Created optimized initial floorplans targeting 70 percent area utilization, 20 percent power distribution, and 10 percent signal integrity improvement using Cadence Innovus, considering congestion and hierarchical partitioning strategies-Executed block placement, pin assignment, and physical constraint development to maintain under 3 percent interconnect delay impact, enabling effective integration with backend power planning and clock tree synthesis (CTS) teams-Conducted early DRC and LVS checks using Calibre with an error rate below 0.5 percent, proactively resolving design rule violations and preparing detailed physical verification and compliance reports for signoff readiness-Coordinated weekly status updates and milestone tracking with project managers, ensuring transparent reporting on design progress, risks, and deliverables for on-time execution.
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