Bhargav Kuppala
SoC Physical Integration & Full Chip PV Convergence @ Intel
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Bhargav Kuppala
Passionate about driving innovation in SOC design and Physical Verification, I bring over…
Experience
Soc Design Engineer
Dec 2019 — Present · Bengaluru, IN
As the SoC Design Engineer at Intel, I oversaw the definition, design, verification, and documentation for SoC (System on a Chip) development. Some achievements during my time at Intel include- Led Full Chip layout convergence, collaborating across teams (Package, PDN, Floorplan, RV/EM).Innovated high-speed design solutions with structural/Custom routing push down- Developed RDL routes template, managed RDL routing for Intel & TSMC designs, automated RDL route completion- Managed MIMCAP designs, developed specs, oversaw integration with subsystems/IPs- Owned SoC/FC LV integration, managed collaterals, checks, and waivers- Supervised layout verification, triaged LV issues, supported latch-up and ESD checks- Implemented spare cells, addressed DRC violations with automation- Improved Metal Fill quality, prepared DRC fix tcls- Oversaw ASIC block implementation from synthesis to GDS- Managed MACRO cell distribution, ensured proper routing, enhanced layout efficiency, improved QOR.*Awards- I received at Intel: Received 4 Divisional Recognition Awards for my projects Technologies: Technologies: 18A,Intel 7, Intel 10, TSMC N5, TSMC N7, TSMC 55nm
Education
S.V. University
BSc , Electronics & Computers
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