Bhargav Kesani

About Bhargav Kesani

Experienced Analog Layout Engineer with over 5 years in the VLSI industry, specializing in full-custom layout design for analog and mixed-signal integrated circuits across technology nodes from 180nm down to advanced 3nm and 1.8nm (Intel RibbonFET). Proficient in area estimation, floor planning, matched device placement (common-centroid/interdigitated), MIM capacitor integration, and IP-level layout assembly. Adept at collaborating with circuit designers to deliver high-quality, DRC/LVS-clean layouts on schedule. Skilled in debugging and resolving complex physical verification issues including DRC, LVS, Antenna, Density, and EM/IR. Strong hands-on experience with industry tools such as Cadence Virtuoso, Calibre, ICV, CPDS, and version control systems like Cliosoft and IC Manage. Known for driving layout quality, mentoring team members, and efficiently executing ECOs with minimal design impact.

Experience

1. Senior Analog Layout Engineer

   Intel

   Mar 2024 — Present · Houston, TX, US

   Designed and taped out analog blocks in 18Anm technologies, achieving high matching accuracy with common-centroid and interdigitated layout techniques.• Collaborated with circuit designers to optimize layout for performance and area, ensuring first-pass success with DRC, LVS, and ERC checks using Calibre.• mentoring junior layout engineers and interns in layout practices and review procedures.

Education

• Lamar University

  Master's degree

  2022 — 2024

• Jawaharlal Nehru Technological University

  Bachelor of Engineering - BE

  2016 — 2020