Bharath S
- Role
- Senior Design & Verification Engineer at NXP Semiconductors
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Bharath S
Experienced in FPGA Design using VHDL, Proficient in Verification using System Verilog…
Experience
Senior Design & Verification Engineer
Jan 2015 — Present
Skills
- Assembly Language
- Systemverilog
- Embedded Systems
- Coverage Driven Verification
- Hdl - Vhdl,Verilog
- Tcl
- Verilog
- Fpga Prototyping
- Field-Programmable Gate Arrays (Fpga)
- Static Timing Analysis
- Testing
- Apb
- Vlsi
- Application-Specific Integrated Circuits (Asic)
- Assertions
- Methodologies - Vmm,Erm
- Simulations
- Specman
- Fpga
- Formal Verification
- Certitude
- Eda
- Functional Verification
- C
- Integrated Circuit Design
- Vmm
- Rtl Design
- Hvl - System Verilog,Specman-E
- Asic
- Soc
- Modelsim
- Vhdl
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