Bharath Kumar Changala
Physical Design Trainee @Takshila Institute Of Vlsi Technologies
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WORK HISTORY
Physical Design Trainee @Takshila Institute Of Vlsi Technologies
Project Title: ORCA_TOPDuration: May\'23 -Oct\'23I had the privilege of working on an intensive project during my time at Takshila VLSI Institute, focusing on pnr and Timing closure. This hands-on experience allowed me to apply theoretical knowledge gained in the classroom to real-world challenges in the field of physical design.Key Responsibilities:^ Chip Design and Layout: Led the design and layout of specific blocks ensuring adherence to industry standards and best practices.^ Timing Closure: Implemented strategies for timing closure, optimizing clock networks, and resolving timing violations to enhance overall chip performance.^ Power Optimization: Executed power optimization techniques, contributing to the development of energy-efficient designs.^ Tool Proficiency: Developed proficiency in Synopsys ICC,Primetime employing them for tasks such as PNR and Timing Closure.##This project was a significant learning experience, allowing me to deepen my understanding of timing closure, power optimization. I honed my ability to work effectively in a team, communicate technical concepts, and adapt to the dynamic nature of semiconductor projects.##The experience gained from this project has solidified my passion for physical design in VLSI. I am eager to apply these skills and insights in my professional journey, contributing to the advancement of semiconductor technology.
EDUCATION
JNTU Anantapur
Bachelor of Technology - BTech
ABOUT BHARATH KUMAR CHANGALA
Hello LinkedIn community!>>I am a electronics graduate and trained VLSI…
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