Bharath Juluri

About Bharath Juluri

I am an ASIC Design Sr.Engineer at Synopsys, a global leader in electronic design automation and semiconductor IP. I am currently working on RISC-V based processors, verifying new features and developing new flows for coverage closures. In my current role, I have been involved in several significant projects, such as the ARC-VPX processor family, which delivers high-performance and low-power solutions for embedded applications.I graduated with a Bachelor of Technology degree in Electrical, Electronics and Communications Engineering from Lovely Professional University in 2021, where I excelled in both academics and extracurricular activities. I participated in multiple technical competitions, such as the Smart India Hackathon - 2019, where I won the first prize for solving a problem statement of Mahendra & Mahendra. I also conducted workshops and events, and published multiple patents, such as an automated system for tyre information and a system for controlling light devices. I have certifications in Algorithmic Toolbox, The Data Scientist\'s Toolbox, and Python Basics for Data Science from Coursera and edX. My core competencies include system verilog, Python, scripting, and processors architecture. I am passionate about learning new technologies and applying them to solve real-world problems. I aspire to become a leading expert in the field of ASIC design and verification.

Experience

1. Hardware Engineer

   IBM

   Nov 2025 — Present · Hyderabad, IN

Education

• Lovely Professional University

  Bachelor of Technology, Electrical, Electronics and Communications Engineering

  2017 — 2021

• TSRJC -SARVAIL

  intermediate education, MPC

  2015 — 2017

• Birla Institute of Technology and Science, Pilani

  Master of Technology - MTech, Embedded systems