Bharath R.

About Bharath R.

Core Competencies:High speed layout design lead, SerDes PHY building blocks (VCO, PLL, CDR, RX, TX, DFE, CTLE)Hands on experience in deep sub micron technologies(7nm,10nm,14nm,40nm,45nm,90nm,130nm,180nm) Layout Tools : Virtuoso –L & XL Editor (Cadence ) & Intel custom tool(Genoa) Process technologies: STMicroelectronics,TSMC,Siltera,Intel Layout Design for various blocks(TX,Rx,clk-lane, PLL,LDO,Rcomp,CTLE,VGA) Physical verification (DRC, LVS and PEX) on Calibre, Hercules (Synopsys) Post Layout Extraction Tools : StarRC (Synopsys) Reliabity check tool:Totem(EM/IR) Power/ground structure, block placement and layout floor planning SKILL SET SUMMARY•Good understanding of CMOS fabrication process•Depth knowledge in Analog Layout high speed serdes Design like pcie gen6,pcie gen5,Type-c USB•Layout Rules for the WPE (Well Proximity Effect)•Debug DRC, LVS and PEX on Calibre•Good understanding on signal flow, Prevention of latch_up Possibilities and Antenna Effect•Good understanding of IR drop issues and all the critical signals•Meet challenges in the high speed signals.

Experience

1. Supv Ams Layout

   Synopsys Inc

   Jun 2021 — Present · Hyderabad, IN

   Layout supervisor for Analog & mixed signal designs

Education

• JNTUH College of Engineering Hyderabad

  Master of Technology - MTech, VLSI SYSTEM DESIGN

  2012 — 2015

• JNTUH College of Engineering Hyderabad

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2007 — 2011