Bharath Kumar
Silicon Lifecycle Monitoring at Synopsys Inc
- Role
- Sr R & d Engineer at Synopsys Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Bharath Kumar
1+ years of experience in DFT - VLSI Domain.DFT test logic implementation includes- Scan Test (Scan Insertion & Stitching and checking DRC rules)-Worked on block level ATPG pattern generation for stuck-at and TDF-Coverage improvement – achieved 99% coverage for stuck-at-Non timing ATPG pattern simulation for both serial & parallel-Coverage analysis and improvement -Having basic Knowledge on STA and Synthesis concepts
Experience
Sr R & d Engineer
Jul 2019 — Present · Hyderabad, IN
Education
Trinity Junior collegeBoard of Intermediate
Intermediate, ipe
2006 — 2008
Tirumala engineering collegeJawaharlal Nehru Technology university
Bachelor's Degree, ECE
2008 — 2012
Skills
- Asic
- Linux
- Logic Synthesis
- Xilinx
- Systemverilog
- Questa
- Atpg
- Verilog
- C Language
- C
- Static Timing Analysis
- Digital Electronics
- Simulations
- Very-Large-Scale Integration (Vlsi)
- Fastscan
- Microsoft Office
- Vlsi
- Rtl Design
- Dft
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