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Bharath Kumar

--Design Verification trainee at VLSI FIRST || 2023 B.Tech(EEE) Graduate .

Role
Verilog Hdl and System Verilog and Universal Verification Methodology at Vlsi First
Location
Hyderabad, TG, IN
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

About Bharath Kumar

Bharath Kumar | RTL Design and Verification Expert | Strong background in digital…

Experience

  1. Verilog Hdl and System Verilog and Universal Verification Methodology

    Vlsi First

    Sep 2023 — Present · Hyderabad, IN

Education

  • Keshava Reddy

    High School Diploma

    2017

  • Jb Institute Of Engineering and Technology

    Bachelor of Technology

    2023

  • Sri Chaitanya Junior College

    High School Diploma

    2019

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Bharath Kumar — Verilog Hdl and System Verilog and Universal Verification Methodology at Vlsi First in Hyderabad, TG, IN | Unifers