Bharath Gonuguntala
ASIC Physical Design Expert | 10+ yrs RTL-to- GDSII & HBM Designs | AI- chip innovator | Synthesis, STA & Low power Design | IR/EM Analysis | 28nm-4nm
- Role
- Senior Physical Design Engineer at Etched
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Bharath Gonuguntala
With over a decade of expertise in ASIC physical design, I have contributed to more than…
Experience
Senior Physical Design Engineer
Jan 2025 — Present · Santa Clara, CA, US
Education
Visvesvaraya Technological University
Bachelor's degree, Electrical and Electronics Engineering
Skills
- C++
- Python
- Fpga
- Asic
- C
- Debugging
- Vhdl
- Semiconductors
- Verilog
- Physical Design
- Soc
- Static Timing Analysis
- Vlsi
- Perl
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