Bharat Patel

About Bharat Patel

Technically advanced engineering professional with 25 years of design experience at Intel/AMD/Broadcom with special expertise in physical design with multi-foundry CAD flows. • Experienced with Managing and Mentoring trans-national and multi-disciplinary teams, and operational collaboration to improve innovation and solve design challenges. • Breadth of knowledge and success completing 15+ tape-out of Microprocessor, ASICs, FPGAs and Server SoCs on TSMC (16nm-3nm) and Intel (65nm-5nm,18A) technology. • Strong result-oriented engineering skills coupled with an aptitude for team building,leadership, and mentorship. Current Instructor of Adv. Physical design at UCSC, CAArea of Expertise: ASIC Design/ SoC Block Design / Full Chip Design – RTL to GDSII / CAD Physical Design flow development and Methodology / Team Leadership and Mentoring / Troubleshooting & Issue Resolution / Timing-Layout Signoffs / AI & Machine Learning Solutions

Experience

1. Teaching Instructor

   Ucsc Silicon Valley Extension

   Sep 2022 — Present · Santa Clara, CA, US

   Teaching Adv. Physical Design course to 10+ students onsite. Conducting lectures and practical labs to teach concepts of RTL-II-GDS Implementation and Signoff flows.

Education

• University of Mumbai

  BE, Electronics

  1992 — 1996

• Penn State Great Valley

  MS, Electrical Engineering

  1996 — 1998

Skills

• Verilog
• Very-Large-Scale Integration (Vlsi)
• Asic
• Mixed Signal
• Circuit Design
• System on a Chip (Soc)
• Hardware Architecture
• Semiconductors
• Debugging
• Logic Synthesis
• Soc
• Physical Design
• Vlsi
• Integrated Circuit Design
• Microprocessors
• Rtl Design
• Static Timing Analysis
• Engineering Management
• Application-Specific Integrated Circuits (Asic)
• Perl
• Embedded Systems
• Eda
• Processors
• Cmos
• Integrated Circuits (Ic)
• Integration
• Ic
• Systemverilog